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| `timescale 1ns / 1ps
module led_water( input clk , input rst_n , output reg [3:0] led ); parameter TIME_S = 26'd50_000_000 ; reg [25:00] cnt_s ; always @(posedge clk) begin if(!rst_n) cnt_s <= 26'd0 ; else if(cnt_s == TIME_S - 26'd1) cnt_s <= 26'd0 ; else cnt_s <= cnt_s + 26'd1 ; end always @(posedge clk) begin if(!rst_n) led <= 4'b1000 ; else if(cnt_s == TIME_S - 26'd1) led <= {led[0], led[3:1]} ; end
endmodule
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