//	key_filter.v
`timescale 1ns / 1ps

module key_filter(
	input			clk		,
    input			rst_n	,
    input			key		,
    output	reg		key_out	
);
    
    parameter	TIME_20MS	=	20'd1_000_000	;
    reg	[19:00]	cnt_20ms	;
    
    always @(posedge clk) begin
        if(!rst_n)
            cnt_20ms	<=	20'd0	;
        else if(!key) begin
            if(cnt_20ms == TIME_20MS - 20'd1)
            	cnt_20ms	<=	cnt_20ms	;
       		else
            	cnt_20ms	<=	cnt_20ms	+	20'd1	;
        end
        else
            cnt_20ms	<=	20'd0	;
    end
    
    always @(posedge clk) begin
        if(!rst_n)
            key_out	<=	1'b0	;
        else if(cnt_20ms == TIME_20MS - 20'd2)
            key_out	<=	1'b1	;
        else
            key_out	<=	1'b0	;
    end
    
endmodule

//	tb.v
//	为方便观察仿真结果，缩小源文件中TIME_20MS = 20'd10
`timescale 1ns / 1ps

module tb();
reg		clk		;
reg		rst_n	;
reg		key		;
wire	key_out	;
    
key_filter key_filter_tb(
    .clk		(clk		),
    .rst_n		(rst_n		),
    .key		(key		),
    .key_out	(key_out	)	
);
    
initial begin
    clk		=	1'b0	;
    rst_n	=	1'b0	;
    #100
    rst_n	=	1'b1	;
end
always	#10	clk	=	~clk;
    
initial begin
	key	=	1'b1	;
    #120
    key	=	1'b0	;
    #240						//	20 * 10 = 200
    key	=	1'b1	;
end
    
endmodule